The present invention relates to a semiconductor memory device and a method of programming the memory device and, more particularly, to an electrically programmable nonvolatile semiconductor memory device, a method of programming the memory, and method of verify reading after programming operation of the memory device.
This application is based on Japanese Patent Application No. 9-203260, filed Jul. 29, 1997 and Japanese Patent Application No. 10-000745, filed Jan. 6, 1998, the content of which is incorporated herein by reference.
As one conventional semiconductor memory device, an electrically programmable EEPROM is known. In an EEPROM, a plurality of memory cell units (e.g., NAND cell unit, NOR cell unit, AND cell unit, or DINOR cell unit) each including a plurality of memory cells are arrayed to form a memory cell array. Of EEPROMS, a NAND cell type EEPROM in which a plurality of memory cells are connected in series to form a NAND cell unit is attracting attention because high-degree integration is possible.
One memory cell unit of a NAND cell type EEPROM has a FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. A plurality of such memory cells are connected in series to form a NAND memory cell unit such that adjacent memory cells share a source and a drain. A plurality of such NAND memory cell units are arranged in a matrix manner to form a memory cell array.
Drains at one end of NAND memory cell units arranged in the column direction of the memory cell array are connected together to a bit line through selection gate transistors. Sources at the other end are connected to a common source line through selection gate transistors. The control gate lines of memory cell transistors and the gate electrodes of the selection gate transistors are connected together as a word line (control gate line) and a selection gate line, respectively, in the row direction of the memory cell.
NAND cell type EEPROMs as described above are disclosed in, e.g.,
K. -D. Suh et al., "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, November 1995 (reference 1), and
Y. Iwata et al., "A 35 ns Cycle Time 3.3 V Only 32 Mb NAND flash EEPROM," IEEE J. Solid-State,Circuits, vol. 30, pp. 1157-1164, November 1995 (reference 2).
A conventional NAND cell type EEPROM disclosed in reference 1 will be described below with reference to FIG. 1 (FIG. 1 of reference 1) and FIGS. 2A and 2B (FIGS. 3A and 3B of reference 1).
FIG. 1 is a block diagram showing the arrangement of the conventional NAND cell type EEPROM. In FIG. 1, reference numeral 10 denotes a NAND cell unit. Reference symbol BSEL denotes a block selection signal; CG.sub.0 to CG.sub.15, common gate lines; WL.sub.0 to WL.sub.15, word lines; BL.sub.0 to BL.sub.4243, bit lines; SSL, a selection gate line on the bit line side; GSL, a selection gate line on the source line side; and S/A, a part (sense amplifier circuit S/A) of a page buffer.
FIG. 2A shows the arrangement of the NAND memory cell unit shown in FIG. 1. FIG. 2B shows the bias states when erase, read, and program operations are performed for the NAND memory cell unit.
In FIG. 2B, "Bulk" denotes a p-type well formed in an n-type semiconductor substrate; and "F", a floating state.
In the NAND cell unit 10 shown in FIGS. 1, 2A, and 2B, a plurality of cell transistors made of n-channel MOSFETs having a floating gate and a control gate are connected in series. Drains at one end are connected to the bit lines BL through NMOS transistors as selection gates. Sources at the other end are connected to a common source line through NMOS transistors as selection gates.
These transistors are formed on the same well substrate. The control electrodes of the memory cells are connected to the word lines WL.sub.0 to WL.sub.15 continuously extending in the row direction. The control gates of selection transistors on the bit line side are connected to the selection gate line SSL. The control gates of selection transistors on the source line side are connected to the selection gate line GSL.
Each cell transistor has a threshold voltage corresponding to stored data. In the case of a NAND flash memory, a state wherein a cell transistor is depletion type (D type) is defined as a data "1" storing state (erased state). A state wherein a cell transistor is an enhancement type (E type) is defined as a data "0" storing state (programmed state). Also, an operation of shifting the threshold voltage of a cell transistor storing data "1" in the positive direction to make the transistor store data "0" is called a "program operation". An operation of shifting the threshold voltage of a cell transistor storing data "0" in the negative direction to make the transistor store data "1" is called an "erase operation".
During the erase operation, the common gate lines CG.sub.0 to CG.sub.15 are grounded. The logic level of-the block selection signal BSEL of a selected block changes to "H" (power-supply voltage). The logic level of a block selection signal of an unselected block maintains "L" (ground potential). Accordingly, each word line of the selected block is set at the ground potential, and each word line of the unselected block is set in the floating state.
Next, a 21-V and 3-ms erase pulse is applied to the bulk (a p-type well of the cell transistor). In the selected block, this erase voltage (21 V) is applied between the bulk and the word line. Electrons in a floating gate flow into the p-type well in the cell due to an FN (Fowler-Nordheim) tunnel current. Consequently, the threshold voltage of the cell becomes about -3 V. Since over-erase is not a problem in a NAND type flash memory, the cell is deliberately erased to have a threshold voltage of about -3 V by one erase pulse.
On the other hand, the unselected block is unaffected by the erase pulse due to capacitive coupling of the word line in the floating state and the p-type well of the cell. The word line in the floating state is connected to the source of a transistor to which the block selection signal BSEL is applied, to a metal wire between this source and a polysilicon word line, and to the polysilicon word line. The capacitive coupling ratio (coupling ratio) between this word line and the channel is calculated from the capacitance connected to the word line in the floating state.
This capacitance includes the source junction capacitance of the transistor, the overlap capacitance of the source and the gate, the capacitance on the field of the polysilicon and the metal wire, the capacitance between the polysilicon word line and the well region (p-type well) of the cell, and the like. Of these capacitances, the capacitance between the word line and the p-type well is dominantly large with respect to the total capacitance. Therefore, the coupling ratio calculated on the basis of results of actual measurements is as large as approximately 0.9. This prevents the FN tunnel current from flowing.
In an erase-verify operation, whether the threshold voltages of all cells in the selected block are -1 V or less is checked.
In a read operation, cell data of one page is simultaneously transferred to a latch circuit of a page buffer (to be referred to as a sense amplifier circuit S/A hereinafter) and continuously read out.
FIG. 3 (FIG. 4 of reference 1) is a timing chart showing the operating waveforms of principal signals when a read operation is performed for the EEPROM shown in FIG. 1.
In sensing cell data of one page, the sense amplifier circuit S/A is first initialized to store "0" data (level "L", a state wherein data has been read out from a programmed cell). At time t1, the bit line is at 0 V, and the selection gate lines SSL and GSL are at 4.5 V.
At time t2, 0 V is applied to a selected word line WL.sub.i in the selected block (NAND cell), and 4.5 V as a pass voltage are applied to an unselected word line WL.sub.i in the selected block. Since 4.5 V applied to the unselected word line are higher than the threshold voltages of each cell after programming operation and erasure, all unselected cells function as pass transistors.
The selected word line to which 0 V is applied turns on only erased cell transistors. Accordingly, a NAND cell unit in which data of an erased cell has been read becomes a verification passed cell whose bit line BL is grounded. A NAND cell unit in which data of a programmed cell has been read sets the bit line BL in an open state.
At time t3, a direct sense path from a bit line to a latch circuit is shut off by changing the control signal PGM in FIG. 1 to "L", so latch data is determined only through a sense transistor. A current load transistor of a PMOS current mirror circuit is activated by a reference voltage Vref to supply a load current of 2 .mu.A to bit lines. This load current flows through a bit line reading out data of an erased cell, so this bit line maintains level "L". A bit line reading out data of a programmed cell changes to level "H".
At time t4, the bit line reading out data of a programmed cell turns on a sense transistor to invert latch data to "1".
In this manner, a latch circuit which has read out data of a programmed cell stores "1", and a latch circuit which has read out data of an erased cell stores "0". These latch data are supplied to a read circuit and converted into normal logic levels. Accordingly, data are simultaneously set to all latch circuits of one page to enable a continuous read operation.
In a program operation, program data is first continuously loaded into a sense amplifier circuit S/A. "0" is cell data for performing programming, and "1" is cell data for inhibiting programming. A program cycle is repeated until cells in columns corresponding to all latch data "0" are programmed.
Each program cycle includes application of a program pulse and a program verify read operation for preventing over-programming of a cell storing "0" data.
More specifically, a 40-.mu.s program cycle includes the following steps.
(1) Bit line set up (8 .mu.s): in accordance with program data in a latch circuit of the sense amplifier circuit S/A, the bit line level is set to 0 V for programming or to Vcc for program inhibition.
(2) Programming (20 .mu.s): a program voltage is applied as a narrow pulse to a selected word line.
(3) Word line discharge (4 .mu.s): a high potential of the selected word line is discharged to prepare for application of a next low verify potential.
(4) Program verify (8 .mu.s): whether the threshold voltage of the programmed cell is programmed to a target value or more is checked.
In the program verify read operation, data in a latch circuit connected to a sufficiently programmed cell changes from "0" to "1" to prevent further programming. Bias conditions during the program verify read operation are nearly identical with those during the read operation. However, programmed data is stored in a latch circuit, and 0.7 V different from 0 V is applied to a selected word line.
Under this condition, when the threshold voltage of the programmed cell exceeds 0.7 V, i.e., when the cell is sufficiently programmed, the data in the latch circuit changes from "0" to "1". A latch circuit storing data "1" is unaffected during the verify operation because data in a latch circuit changes only from "0" to "1".
A program cycle is repeated until all latch circuits in the page buffer store "1" or a maximum programming time of 10 cycles is reached.
FIG. 4 (FIG. 5 of reference 1) shows the bias conditions of a program inhibiting voltage supplied to the channel of a selected cell.
A transistor of the selection gate line SSL on the bit line side is rendered conductive, and a transistor of the selection gate line GSL on the source line side is rendered nonconductive. The bit line of a cell to be programmed is set at 0 V, and the bit line of a program inhibiting cell is set at Vcc. Each channel of memory cells in a NAND cell unit is set at the ground potential by a 0-V bit line.
When a program voltage is applied to the gate of a selected cell, a large potential difference is produced between the floating gate and the channel.
Consequently, electrons are injected into the floating gate by an FN tunnel current, and the cell is programmed.
In a program inhibiting cell, the channel of a selected NAND cell unit is precharged by a Vcc bit line.
When word lines of the selected NAND cell unit, i.e., a selected word line to which the program voltage is applied and unselected word lines to which the pass voltage is applied rise, series capacitances are coupled through the word lines, floating gates, channels, and p-wells of the cells to increase the channel capacitance.
As described above, the channel potential of a program inhibiting NAND cell unit in a selected block is determined by the capacitive coupling of word lines and channels. Therefore, to sufficiently increase the program inhibit potential, it is important to sufficiently charge the channels at initial and increase the capacitive coupling ratio between the word lines and the channels.
A coupling ratio B between word lines and channels is given by: EQU B=Cox/(Cox+Cj)
where Cox is the total sum of gate capacitances between word lines and channels, and Cj is the total sum of junction capacitances between the sources and drains of cell transistors. The channel capacitance of the NAND cell unit is the total of the total sum Cox of the gate capacitances and the total sum Cj of the junction capacitances. The overlap capacitances between selection gates and sources, the capacitances between bit lines and sources/drains, and the like as other capacitances are ignored since they are much smaller than the total channel capacitance. PA1 (a) loading program data into latch circuits of the sense amplifier circuits; PA1 (b) identifying a sense amplifier circuit instructed to perform programming and storing an identification result in a data storing circuit corresponding to the identified sense amplifier circuit; PA1 (c) performing a program operation; PA1 (d) resetting data in the sense amplifier circuit instructed to perform programming to load program data in accordance with the identification result stored in the data storing circuit; PA1 (e) performing a program verify read operation; PA1 (f) determining whether latching data in all the sense amplifier circuits of one page indicate that all the memory cells of one page are completely programmed, ending the program operation if all the memory cells are completely programmed, and returning to step (c) if all the memory cells are not completely programmed. PA1 a memory cell array having data lines and word lines crossing each other and having electrically programmable nonvolatile memory cells arranged at intersections of the data lines and word lines; PA1 sense amplifier circuits connected to the data lines and having a function of reading out and latching data of the memory cell array through sense nodes and a function of loading and latching program data of the memory cell array; PA1 data storing circuits for storing the program data loaded into the sense amplifier circuits; and PA1 reset circuits, where a programming of one page of memory cells selected by the word line is divisionally performed by plural divisional programmings, for resetting the sense amplifier circuits which have been instructed to perform programming by the load data of first to (n-1)th (n is an integer equal to or more than two) divisional programmings at a time of n-th divisional programming to the load data in accordance with the data stored in the data storing circuits. PA1 a memory cell array having data lines and word lines crossing each other and having electrically programmable nonvolatile memory cells arranged at intersections of the data lines and word lines; PA1 sense amplifier circuits connected to the data lines and having a function of reading out and latching data of the memory cell array through sense nodes and a function of loading and latching program data of the memory cell array; and PA1 data storing circuits for storing the program data loaded into the sense amplifier circuits; PA1 wherein a program operation and a program verify read operation are repeatedly performed until first program pass is determined, then the sense amplifier circuits instructed to perform programming are reset to the load data in accordance with the data stored in the data storing circuits, and a program verify read operation is performed again. PA1 a memory cell array having data lines and word lines crossing each other and having electrically programmable nonvolatile memory cells arranged at intersections of the data lines and word lines; and PA1 sense amplifier circuits connected to the data lines and having a function of reading out and latching data of the memory cell array through sense nodes and a function of loading and latching program data of the memory cell array, PA1 wherein if it is determined that memory cells to be programmed have been sufficiently programmed after a program operation and a program verify read operation are cyclically performed, an inverse read operation in which a logic of the sense amplifier circuits is inverted as compared to a normal read operation and in which the word line is set to a voltage which is equal to or higher than a normal read voltage and not higher than a program verify read voltage is performed to reset the sense amplifier circuits to the load data, and a program verify read operation is performed again. PA1 a memory cell array having data lines and word. lines crossing each other and having electrically programmable nonvolatile memory cells arranged at intersections of the data lines and word lines; and PA1 sense amplifier circuits connected to the data lines and having a function of reading out and latching data of the memory cell array through sense nodes and a function of loading and latching program data of the memory cell array, PA1 wherein, after a program operation and before program verify read operation, an inverse read operation in which a logic of the sense amplifier circuits is inverted as compared to a normal read operation and in which the word line is set to a voltage which is equal to or higher than a normal read voltage and not higher than a program verify read voltage is performed to reset the sense amplifier circuits to the load data. PA1 a memory cell array having data lines and word lines crossing each other and having electrically programmable nonvolatile memory cells arranged at intersections of the data lines and word lines; PA1 sense amplifier circuits connected to the data lines and having a function of reading out and latching data of the memory cell array through sense nodes and a function of loading and latching program data of the memory cell array; PA1 data storing circuits for storing the program data loaded into the sense amplifier circuits; and PA1 an erroneous program detecting circuit for reading into the sense amplifier circuits information data indicating that an erroneous program occurred based on a logical combination of the data stored in the data storing circuits during a program operation and data appeared at the sense nodes by a normal read operation or a program verify read operation. PA1 (a) loading data into latch circuits of the sense amplifier circuits; PA1 (b) identifying a sense amplifier circuit instructed to keep erased by the load data and storing an identification result in a storing circuit corresponding to the identified sense amplifier circuit; PA1 (c) performing a program operation; PA1 (d) performing a program verify read operation; PA1 (e) determining whether latching data in all the sense amplifier circuits of one page indicate that all the memory cells of one page are completely programmed, ending the program operation if all the memory cells are completely programmed, and repeatedly performing the program operation and the program verify read operation if all the memory cells are not completely programmed; and PA1 (f) determining whether the erroneous program occurred after ending of the program operation based on a logical combination of the identification result stored in the storing circuit and program verify read data read out by the sense amplifier circuit.
FIG. 5 shows prior art of a peripheral core circuit of a sense amplifier circuit S/A. FIG. 6 is a timing chart showing a program operation and a program verify read operation of the circuit.
In FIGS. 5 and 6, reference symbols LOAD, SBL, DCB, BLSHF, .phi..sub.latch1, and .phi..sub.latch2 denote control signals supplied to a sense amplifier circuit S/A; and N.sub.sense, a bit line potential sense node.
Referring to FIG. 5, the sense amplifier circuit S/A comprises a p-channel transistor M2 as a constant-current source, an n-channel transistor M1 for bit line potential clamping, a latch circuit LT, an n-channel transistor M3, a transfer gate NMOS transistor M4 for sense amplifier circuit S/A resetting, an NMOS transistor MS for forcibly inverting the data in the sense amplifier, an NMOS transistor M7 for sensing, and an NMOS transistor M6 for inverse read latch control. The p-channel transistor M2 charges the bit line BL for a predetermined period on the basis of a precharge control signal LOAD (corresponding to an output CM.sub.out of the current mirror circuit shown in FIG. 1). The n-channel transistor M1 is inserted in series into the bit line BL and has a gate to which a control voltage BLSHF is applied. The latch circuit LT latches memory cell data read out to a sense node N.sub.sense between the p-channel transistor M2 and the n-channel transistor M1.
The n-channel transistor M3 discharges electric charge in the sense node N.sub.sense for a predetermined period on the basis of a discharge control signal DCB. The NMOS transistor M4 is inserted between the sense node N.sub.sense and a second storage node Q of the latch circuit LT and has a gate driven by a control signal SBL. The NMOS transistor M5 is connected between a first storage node /Q ("/" indicates inversion in the remainder of this specification) of the latch circuit LT and a ground potential and turned on by a first data latch control signal .phi..sub.latch1 applied to its gate for a predetermined period. The NMOS transistor M7 is connected in series with the NMOS transistor M5 between the first storage node /Q of the latch circuit LT and the ground potential and has a gate connected to the sense node N.sub.sense. The NMOS transistor M6 is connected in series with the NMOS transistor M7 between the first storage node /Q of the latch circuit LT and the ground potential and turned on by a second data latch control signal (inverse read latch control signal) .phi..sub.latch2 applied to its gate for a predetermined period.
The latch circuit LT is a flip-flop circuit in which the input nodes and output nodes of two CMOS inverter circuits IV1 and IV2 are cross-coupled (inversely connected in parallel).
In this arrangement, the input node (first storage node /Q) of the first CMOS inverter circuit IV1 is an sense amplifier inverting signal input node. The input node (second storage node Q) of the second CMOS inverter circuit IV2 is connected to an input/output circuit I/O through a data bus and functions as a reset node.
Read, erase, and program operations of the sense amplifier circuit S/A shown in FIG. 5 will be described below.
In a normal read operation of the EEPROM, the transistors M3 and M4 are turned on for a predetermined period to reset the latch circuit LT, setting the nodes Q and /Q at "L" and "H", respectively. After that, the bit line BL is charged by a constant current from the transistor M2. While the constant current is kept flowed, the bit line is discharged by a cell current ICELL generated in accordance with the level of the threshold voltage of the cell transistor. When a predetermined time elapses, the transistor M5 is turned on.
If data "1" is read out from the NAND memory cell unit to the bit line BL, a cell current flows. Then, the bit line potential lowers, the transistor M7 is kept OFF, and the node /Q remains level "H" as the reset state of the latch circuit LT. Conversely, if data "0" is read out from the NAND memory cell unit to the bit line BL, no cell current flows. The bit line potential is kept at level "H", the transistor M7 is turned on, and stored data in the latch circuit LT is forcibly inverted. Consequently, the nodes /Q and Q change to levels "L" and "H", respectively. Data in the node Q of the latch circuit LT corresponding to a selected column is read out to the input/output circuit I/O through the data bus.
When the EEPROM is to be erased, the sense amplifier circuit S/A is used in an erase verify read operation. In this operation, the sense amplifier circuit S/A operates in the same manner as in the normal read operation. If the cell transistor is erased (if data "1" is stored), the nodes /Q and Q change to levels "H" and "L", respectively. Conversely, if the cell transistor is not erased (if data "0" is stored), the nodes /Q and Q change to levels "L" and "H", respectively. Since it is determined that the erase is incomplete if even one of the nodes Q of all the sense amplifier circuits simultaneously operating is level "H", an erase restart signal is output to restart the erase operation on the basis of this data.
When the EEPROM is to be programmed, program/unprogram data is applied to input data from the data bus to the node Q of the latch circuit LT corresponding to a selected column. If data "0" is input, the node Q changes to level "L". If data "1" is input, the node Q changes to level "H". When the transistor M4 is turned on, the data in the node Q is transferred to the bit line BL through the transistor M4. During the program operation, the channel in the selected memory cell is booted to an intermediate potential. Thus, the cell is programmed if data "L" is applied to the bit line BL. However, it is not programmed if data "H" is applied.
To obtain a high-speed, high-reliability EEPROM, it is necessary to narrow the cell transistor threshold voltage distribution after programming operation. As described previously, whenever programming is performed the programmed data is read out (program verify read) and compared with the data to be programmed. If the data is insufficiently programmed, programming is continued. When the programmed data agrees with the data to be programmed, programming is complete.
In this program verify read operation, a conventional approach is to perform a read operation with program data stored in the sense amplifier circuit S/A without resetting the latch circuit LT. This program verify read operation is the same as a normal read operation except that no reset operation for the latch circuit LT is performed.
The nodes Q of the latch circuits LT corresponding to unprogrammed cells to be kept erased and programmed cells which is changed to programmed state from erased state change to level "H". The node Q of the latch circuit LT corresponding to an insufficiently programmed cell of which programming is not completed changes to level "L". Therefore, only an insufficiently programmed cell can be reprogrammed by using the data in the node Q as it is.
Also, a verify voltage (reference voltage) Vref (&gt;0 V) is applied to a selected word line in the program verify read operation, whereas 0 V is applied to a selected word line in the normal read operation. Therefore, cell transistors having threshold voltages between 0 V and Vref are reprogrammed until the minimum value of the threshold voltage distribution after programming operation becomes equal to or higher than the verify voltage (reference voltage) Vref. In this manner, a sufficient margin of programming variation for a given read voltage is assured.
The sense amplifier circuit S/A shown in FIG. 5, however, has a problem caused by a rise in the source-side potential (e.g., the ground potential) resulting from a voltage drop in the resistance component of the common source line which is formed of a diffusion layer or the like. This problem will be described in detail below.
The speeds of operations such as program/erase of an EEPROM are lower than those of a DRAM. To perform high-speed program/read, a page program method or a page read method is often used. In the page program method, program data is simultaneously programmed (in units of pages) from a plurality of column lines into a plurality of memory cells connected to the same row line (word line). In the page read method, stored data are simultaneously read out from a plurality of memory cells connected to the same row line (word line) to a plurality of column lines and sensed/amplified (read out in units of pages).
A program verify read operation when page programming is performed for this EEPROM will be described below.
Assume that the page size is 512 columns, all cells before programming are in an erased state, and only one cell transistor with a very high programming speed exists. Assume also that the cell with a high programming speed is programmed to have a threshold voltage of about 0 to 1 V and the threshold voltages of the other cells are decreased to 0 V or less by first programming.
If verification is performed in this state, a cell current flows in cells in 511 columns except for the very fast programming cell. A voltage drop takes place by the parasitic resistance component of a connection wiring (e.g., a diffusion layer) on the source side of a NAND memory cell unit, and the ground potential rises.
The cell with a high program speed in this state reduces the cell current due to the rise of the ground potential (and also increases the apparent threshold voltage due to a back bias effect resulting from the rise of the ground potential). This cell appears to be sufficiently programmed (i.e., the threshold voltage appears to have become higher than the actual threshold voltage) even if the cell is not sufficiently programmed. Consequently, it is erroneously determined by the verify operation that the cell with a high program speed is completely programmed.
When a page read is performed after all cells are completely programmed, however, most cells are programmed and hence no cell current flows. Therefore, the ground potential does not rise.
Accordingly, in a read operation with no ground potential rise, a cell current in the cell with a high program speed appears to flow easier than in a verify operation after the first programming. Consequently, although the cell with a high program speed is found to be completely programmed as described above, the cell may not have been sufficiently programmed to result in incomplete programming.
This problem will be described in detail below.
First, when a program command is externally input to the chip, a program operation is started. The control signals BLSHF and DCB change to Vcc, and the bit lines BL are grounded (the bit line potential is reset). Before program data is loaded into the sense amplifier circuits S/A, the control signal LOAD changes to Vss, the control signal .phi..sub.latch1 changes to Vcc, and data in the sense amplifier circuits S/A are reset.
That is, the nodes Q and /Q of the latch circuits LT in all the sense amplifier circuits S/A of one page are reset to Vcc and Vss, respectively.
Next, program data is loaded from the input/output circuit I/O through the data bus and latched by the latch circuit LT in each sense amplifier circuit S/A. The nodes Q and /Q are set to Vcc or Vss, respectively, or vice versa in accordance with the data. That is, the node Q is set at Vss in a sense amplifier circuit S/A used for programming a memory cell. The node Q is set at Vcc in a sense amplifier circuit S/A not for programming the memory cell.
Subsequently, the bit lines BL are started to-be charged on the basis of the data latched in the latch circuit LT. That is, the bit line BL to be programmed stores potential Vss, and each bit line BL not to be programmed is charged to Vcc. One of the word lines WL.sub.0 to WL.sub.15, e.g., the word line WL.sub.2 is selected and used to program so that this word line WL.sub.2 rises to a program voltage Vpgm (about 20 V), and the other word lines change to a voltage Vpass (about 10 V). By this operation, a memory cell CELL.sub.2 is programmed as described earlier.
After the programming, a program verify read operation is started. That is, the word line WL.sub.2 used in the programming changes to a verify voltage (reference voltage) Vref (about 0.5 V). The other word lines change to a read voltage Vread (about 4.5 V).
The control signal LOAD to be applied to the gate of the load transistor M2 is controlled to about 1.8 V to balance the load current with the memory cell current. In this state, a read operation is done.
For example, the cell current in an erased memory cell is at least around 2 .mu.A so that the current of the load transistor is set to about 1.5 .mu.A in accordance with the cell current.
Accordingly, no cell current flows in a programmed memory cell, i.e., in a memory cell whose threshold voltage is higher than the verify voltage (reference voltage) Vref (about 0.5 V), so the potential of the bit line BL rises. If the bit line BL is charged to Vcc, the read time becomes long. Therefore, the control signal BLSHF to be applied to the gate of the high-voltage MOS transistor M1 is clamped to, e.g., 1.8 V. Consequently, if the potential of the bit line BL rises to, e.g., 0.9 V, the transistor M1 is cut off, and the sense node N.sub.sense changes to Vcc.
When the sense node N.sub.sense changes to Vcc, the data latch signal .phi..sub.latch1 changes to Vcc. When the sense node N.sub.sense is Vcc, i.e., when a cell found to have a threshold voltage higher than the verify potential Vref is read out, the nodes /Q and Q change to Vss and Vcc, respectively, because the sense node N.sub.sense is Vcc.
In a sense amplifier circuit S/A not for programming, the node Q is preset to Vcc. Therefore, programming is complete when the potentials of the nodes Q in all the sense amplifier circuits S/A of one page change to Vcc.
If, however, a memory cell is insufficiently programmed in a sense amplifier circuit S/A used for programming, the sense node N.sub.sense remains Vss. Therefore, the latch circuit LT is not inverted, and the node Q maintains Vss.
The problem in the above conventional program operation and program verify read operation will be described below with reference to FIGS. 7 and 8.
Assume that programming is performed through, e.g., the word line WL.sub.15 in FIG. 7. Assume also that all of memory cells CELL.sub.i1 to CELL.sub.i5 are so programmed as to increase their threshold voltages.
Memories have process variations in fabrication, so the coupling ratios and the like of memory cells are different. For example, assume that the memory cell CELL.sub.i5 has a larger coupling ratio than those of the other memory cells and hence is programmed faster.
In a verify read operation after programming operation, the other memory cells are erased.
Therefore, the potential of a source node S.sub.i5 of the memory cell CELL.sub.i5 rises due to memory cell currents and resistance components R.sub.0, R.sub.i1, R.sub.i2, . . . , of source lines. The level of rise depends upon cell currents I.sub.CELLi1 to I.sub.CELLi4 and the resistance components and is represented by I.sub.CELLi1 .times.R.sub.0 +I.sub.CELLi2 .times.(R.sub.0 +R.sub.i1)+I.sub.CELLi3 .times.(R.sub.0 +R.sub.i1 +R.sub.i2)+I.sub.CELLi4 .times.(R.sub.0 +R.sub.i1 +R.sub.i2 +R.sub.i3).
Consequently, even when verify voltage (reference voltage) Vref =0.5 V, if the potential of the source node S.sub.i5 of the memory cell CELL.sub.i5 is about 0.5 V, it is determined by verify read that the memory cell CELL.sub.i5 is programmed even though the threshold voltage of the memory cell CELL.sub.i5 is nearly 0 V.
When the memory cells CELL.sub.il to CELLi.sub.4 are programmed after the memory cell CELL.sub.i5 which is programmed faster than the other cells is completely programmed, the threshold voltages of the memory cells CELL.sub.i1 to CELL.sub.i4 take positive values.
In a subsequent read operation, therefore, the potential of the source node S.sub.i5 of the memory cell CELL.sub.i5 does not rise to I.sub.CELLi1 .times.R.sub.0 +I.sub.CELLi2 .times.(R.sub.0 +R.sub.i1)+I.sub.CELLi3 .times.(R.sub.0 +R.sub.i1 +R.sub.i2)+I.sub.CELLi4 .times.(R.sub.0 +Ri.sub.1 +Ri.sub.2 +Ri.sub.3) unlike when the memory cell CELL.sub.i5 alone is initially programmed.
Consequently, the threshold voltage of the memory cell CELL.sub.i5 is read out to Vref or less. As shown in FIG. 8, therefore, the distribution of threshold voltages after programming operation produces a distribution foot of threshold voltages lower than the verify voltage (reference voltage) Vref. If data programming is insufficient, it is sometimes determined in a later read operation that these memory cells are erased cells, resulting in low reliability.
In one known method of reducing the influence of the resistance components of source lines as described above, contacts with metal source wirings are formed in the middle of diffusion layer source lines to thereby increase the number of contacts. Unfortunately, in this method an increase in the pattern area resulting from the increase of the contacts is no longer negligible.
In a NAND cell type EEPROM, it is possible to divide one page into a plurality of groups and program the page by programming a plurality of number of times, i.e., a divisional program scheme is permitted. For example, one page of a 64-Mbit NAND cell type EEPROM has 528 bytes (512 bytes +16 bytes) including 16 bytes of ECC (redundancy bits for error bit check and correction). When page programming is performed by this scheme, it is possible to divide one page into nine groups in units of 64 bytes and program 528 bytes in units of 64 bytes either sequentially or at random.
This scheme is effective when a mass of data to be handled by a user is smaller than 512 bytes.
FIG. 9 shows a part of a memory cell array to explain a divisional program operation in an EEPROM.
Assume that columns of one page selected by the same word lines are divided into first to ninth groups to sequentially program 528 bytes of the page. First, only columns in the first group are selected, and program data is loaded into, e.g., a 64-byte sense amplifier circuit S/A corresponding to this group (unprogram data is loaded into other sense amplifier circuits) to perform first divisional programming. Next, only columns in the second group are selected, and data is loaded into a 64-byte sense amplifier circuit S/A corresponding to this group to perform second divisional programming. A similar operation is repeated to completely program 528 bytes while the columns to be selected are changed.
Even in this divisional programming, however, the problem as described previously arises. That is, the source line of a memory cell initially programmed in divisional programming appears to rise.
The reason for this is as follows. Since all memory cells which are not initially programmed in divisional programming are erased, memory cell currents flow in all memory cells of these NAND cell units.
Consequently, even though the threshold voltage of a memory cell initially programmed in divisional programming is lower than the verify voltage (reference voltage) Vref, this memory cell is determined as a program pass in a program verify read.
This problem is attributed to the conventional circuit itself. That is, in the conventional circuit shown in FIG. 5, a sense amplifier circuit S/A once found to be sufficiently programmed is not subjected to program verify determination in the next cycle; the program verify determination result is not updated.
As one method of avoiding this problem, it is proposed to use a storing circuit for storing program data, a storing circuit for storing verification result data, and a comparator for comparing these data.
If, however, these two storing circuits and the comparator as described above are formed in the chip, the chip area increases to increase the chip cost. On the other hand, if these two storing circuits and the comparator are provided outside the chip, the load on the system outside the chip increases. Additionally, the program time cannot be shortened because comparison data are exchanged between the chip and the external system.
A column circuit in a conventional EEPROM in which two storing circuits and a comparator as described above are formed in a chip will be briefly described below with reference to FIG. 10.
In FIG. 10, reference symbol REG-NTOGL denotes output data from a register (not shown) storing program data; Output, program verification result data; and
N-Input, data of comparison result of REG-NTOGL with Output.
First, the output data REG-NTOGL from the register storing program data is stored as data REG-NQ in a register (not shown) and also applied as the comparison result data N-Input to the gate of a transistor T15.
The comparison result data N-Input changes to level "L" when programming is to be performed and to level "H" when the erased state is to be maintained.
The comparison result data N-Input is at level "L" on a bit line BL to be programmed. Accordingly, an output T5 from an inverter including transistors T13 and T14 and the transistor T15 changes to level "H". The output T5 from this inverter is applied to an inverter T6. An output T4 from the inverter T6 is applied to a NOR gate T3 for bit line programming. A transistor T1 for bit line programming is driven by an output from the NOR gate T3 and applies a program voltage Vpp-Vth to the bit line to be programmed. Vth is the gate threshold voltage of the transistor T1.
On the other hand, the comparison result data N-Input is at level "H" on a bit line BL not to be programmed. Therefore, the transistor T1 for bit line programming is not driven and maintains the ground level, so no programming is performed.
After the programming, verify read is performed.
Consequently, the bit line BL through which the data of the programmed memory cell is read out changes to level "H", and the bit line BL through which the data of the erased memory cell is read out changes to level "L".
Conversely, the program result output data Output changes to level "L" on the bit line BL through which the data of the programmed memory cell is read out data of and to level "H" on the bit line BL through which the data of the erased memory cell is read out.
Next, the program result output data Output is compared with the output data REG-NTOGL from the register storing the program data, and the comparison result data N-Input is updated. In this manner, the program operation and the program verify read operation described above are repeated.
Unfortunately, the circuit as described above requires the registers for storing program data and comparison result data in addition to a sense amplifier circuit S/A. This increases the chip area. Especially in a NAND cell type EEPROM, adding two such registers to all of sense amplifier circuits S/A of one page or 528 bytes increases the chip area and the chip cost.
In the conventional NAND cell type EEPROM as described above, if a memory cell with a high program speed exists in a plurality of memory cells, the potential of a common source line of these memory cells rises when a verify read operation is performed after programming operation or when a page divisional program operation is performed. In addition, the potential of the common source line during the verify operation after programming operation rises to a different extent from that during a normal read operation. This results in incomplete programming.
Also, in the conventional NAND cell type EEPROM as described above, erroneous program sometimes occurs although the probability is low. Erroneous program means that when page programming is performed, data "0" is erroneously programmed in a memory cell which is intended to be kept erased in one selected page. This erroneous program occurs when the channel potential is not controlled as expected by capacitive coupling with a word line. Examples are a case wherein the initial charge potential (Vcc in FIG. 2B) of a bit line connected to a memory cell to be kept erased is insufficient, a case wherein the capacitive coupling ratio of a word line to a channel is small, and a case wherein the node of a channel has a leak path. In any of these cases, the channel potential does not sufficiently rise due to the capacitive coupling with a word line. Consequently, electrons are erroneously injected to cause erroneous program.
In the conventional NAND cell type EEPROM, this erroneous program cannot be detected even if program verify read operation is performed. This is so because a conventional sense amplifier circuit S/A is not so designed as to be able to detect such erroneous program.
This will be described in detail below with reference to FIG. 5.
A program operation and a verify read operation of this sense amplifier circuit S/A shown in FIG. 5 will be briefly described below. In accordance with program data "0" or "1", an I/O line supplies Vss or Vcc to a node Q of the latch circuit. A connection node of NMOS transistors M4 and M1 connected in series, which connects the node Q to a bit line BL, is a sense node N.sub.sense. A charge PMOS transistor M2 and a discharge NMOS transistor M3 are connected to the sense node N.sub.sense and the sense node N.sub.sense is precharged to Vcc when programming is to be performed. When the NMOS transistors M4 and M1 are turned on, data in the node Q is supplied to the bit line BL.
By the aforementioned program operation, a selected memory cell connected to a bit line to which data "0" is supplied is programmed to become E-type. A memory cell connected to a program inhibiting bit line to which data "1" is supplied is stored in a D-type erased state.
In verify read operation, a verify voltage (reference voltage) for threshold detection is applied to word lines of a selected page. As in a normal read operation, whether a memory cell is conducting or not is detected. Since a memory cell in which "0" is programmed does not conduct, a bit line does not lower the sense node N.sub.sense when the NMOS transistor M1 is turned on. Therefore, the sense node N.sub.sense charged to Vcc by the PMOS transistor M2 during this period turns on a NMOS transistor M17. At this time, an NMOS transistor M5 is turned on by a control signal .phi..sub.latch1 Therefore, the node /Q is grounded when the NMOS transistor M7 is turned on. Consequently, the latch circuit is forcibly inverted, and the loaded value Vss of the node Q is changed to Vcc. Meanwhile, since a program inhibited memory cell conducts, the sense node N.sub.sense is discharged through the bit line, and the NMOS transistor M7 is turned off. Accordingly, the latch circuit is not inverted, and the node Q maintains the loaded value Vcc.
If an insufficiently programmed memory cell exists in the selected page, a sense amplifier circuit S/A whose node Q is not inverted to Vcc in verify read operation remains. Therefore, the data program and verify read operations are repeated, and programming is complete if it is determined that the nodes Q of all the sense amplifier circuits S/A have changed to Vcc.
In the conventional sense amplifier circuit S/A shown in FIG. 5 with the above described program/verify read method, programming is complete when the node Q of the latch circuit changes to Vcc in both of a programmed memory cell (including an erroneously programmed memory cell which is supposed to be kept in a program inhibited state, i.e., an erased state) and a memory cell which is kept erased in accordance with a program inhibiting instruction. That is, the conventional circuit has no erroneous program detecting function.
In the conventional EEPROM as described above, erroneous program cannot be detected because the erroneous program is passed during verify read operation. This problem is conventionally solved by providing an error checking/correcting circuit (ECC circuit) inside or outside the EEPROM chip. However, error check requires an extra time, and the chip size increases if the ECC circuit is provided inside the chip. Even if the ECC circuit is provided outside the chip, the system cost increases.